RaceEL

RaceEL

Learn from industry leaders and experienced professionals who bring real-world insights to the classroom

Interview Questions

Signal Integrity

  1. Difference between lumped port and wave port
  2. How to reduce crosstalk.
  3. How to do preprocessing and postprocessing.
  4. How you will optimise your anti pad.
  5. How you will optimise your via.
  6. Explain the process that how you simulate in HFSS.
  7. About raise time.
  8. About impedance matching.
  9. How you will arrange your stackup for 8 layers.
  10. Explain about crosstalk.
  11. If you are simulating with frequency sweep with10 MHz to 6 GHz, and with10 MHz to 20 GHz with same solution frequency. If we simulate it for both cases What type of parameters, you will look for and what is difference in results.
  12. How my raise time will effect my impedance.
  13. About connector modelling
  14. How you will give excitation in HFSS
  15. Which boundary conditions will use in HFSS
  16. Tell about meshing
  17. Tell about solution frequency and frequency sweep
  18. About stackup
  19. What information S parameters have
  20. About 4 port network
  21. About Via and how to optimise the VIA
  22. How impedance will effect by geometry changes.
  23. Explain about reflections when you are having different impedances.
  24. Explain About skin effect.
  25. Explain about crosstalk.
  26. Explain about IL and RL.
  27. What is jitter and causes of jitter.
  28. How width and thickness Will effect the impedance.
  29. Time domain waveform of IL
  30. Frequency spectrum of square wave and degraded square wave.
  31. Explain about via optimization.
  32. Advantages of differential pair.
  33. What happened if you are having impedance discontinuity.
  34. How crosstalk and reflection Will effects the jitter.
  35. What are the main points you will suggest during layout review?
  36. What was the clock frequency? how do you decide on the stub length?
  37. Why do we need terminations? Explain series and parallel termination.
  38. What are reflections? how do you avoid?
  39. Have you worked on stackup design and what were your inputs?
  40. How did you design stackup, whether 16 /12/14 layers are used, how you conclude based on what parameters?
  41. Explain stripline, microstrip and dual stripline.
  42. Which dielectric material you used and how do you decide the material, like what parameters required to decide the dielectric material, explain with FR4 material.
  43. What is X Talk, FEXT, NEXT? How do you reduce X Talk?
  44. What are the interfaces are there on your board. Except DDR interface, what are other interfaces and explain.
  45. Types of clock interfacing logics.
  1. During clock interface have you come across AC coupling and DC coupling.
  2. Have you used any Jitter cleaners?
  3. DDR3 which topology is used; mention signal names routed by using this topology.
  4. How did you connect address lines.
  5. Advantages of flyby topology.
  6. Star topology and Flyby topology difference?
  7. What exactly you will check in DDR3 timing simulations.
  8. Why did you simulate in ANSYS not in HYPERLYNX?
  9. Did you suggest any ODT values for DDR3 data signals?
  10. What is DDR Data length from TX to RX?
  11. Have you worked with SERDES INTERFACE.
  12. Explain about PCIE interface.
  13. Where did you use equalization, like only at TX end or RX end. and where do you add gain TX or RX.
  14. Explain equalization techniques used at TX side gain TX side.
  15. Eye width and height requirement for PCIE gen3.
  16. Are you familiar with differential via model?
  17. Have you designed any via by yourself or you extracted from the existing board?
  18. What all did you do in prelayout simulation?
  19. Explain about connectors like back plain connectors.
  20. Have you reviewed constraint manager in layout? And which layout review tool you used?
  21. What are the tools you are aware?
  22. Which scope and probe you used to check 1GHz clock on board?
  23. Which equipment is used to measure the ripple voltage or power noise?
  24. What is the Oscillator frequency bandwidth.
  25. What is the total thickness of the stackup?
  26. Why stackup are always symmetric? Is there any existence of asymmetric stackup?
  27. Does signal travel faster in microstrip or stripline?
  28. What is loss tangent?
  29. Explain skin effect?
  30. What are the high-speed dielectric materials used?
  31. What is near end crosstalk and far end crosstalk?
  32. What is IBIS? Is IBIS model or SPICE model efficient? Explain.
  33. What is SERDES?
  34. Name some high-speed serial communications.
  35. What is the need for SI?
  36. What is DDR? What is the latest version and its speed?
  37. What are the routing topologies used for high speed?
  38. What is USB? What is the latest version and its speed?
  39. What are the types of terminations? What are the advantages and disadvantages of serial and parallel terminations?
  40. What is driver impedance?
  41. What are the parameters that affect the impedance of the stackup?
  42. What is the difference between bit rate and baud rate?
  43. What is AMIE model? Explain.
  44. What is ground bounce?
  45. What are S-parameters?
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