DDR2/DDR3/DDR4/DDR5

 Module 1: Introduction and Outline  
- Intro to the course, outline and objectives
 Module 2: System Architecture
- Shows where DRAM fits in traditional and non-traditional computer systems
 Module 3: Intro to DRAM
- Discusses the history of DRAM and the pros / cons of DRAM vs SRAM, also describes DRAM cell architecture
 Module 4: DRAM Device Architecture
- Shows how the evolution of DRAM arrays and banks which leads into addressing data within a DRAM array; Defines banks, ranks and channels; Walks through the evolution of DRAM architecture (SDR, DDR1, DDR2, DDR3, DDR4, DDR4 and then on to LPDDR3, LPDDR4 and LPDDR5)
 Module 5: Packaging and HBM
- Introduces different package types (BGA, PoP, 3D Stacking, Die Stacking, TSI and Hybrid Memory Cube); Provides a brief discussion of High Bandwidth Memory (HBM)
 Module 6: DRAM Controller Basics and Addresses
- Discusses required blocks of a DRAM controller (address and control mux, refresh timer, PLL, timing generator, control registers, read and write buffer and IO buffer pads); Describes the translation necessary from system address to DRAM addressing, including symmetric vs asymmetric schemes and NUMA
  Module 7: DDR4 Device and DIMM Pin Descriptions
- Provides a description of the DDR4 device and DIMM pin groups as well as discusses changes in the JEDEC documentation styles to help avoid confusion when reading the standards

  Module 8: Intro to DIMMs (Dual Inline Memory Modules)
- Walks through the evolution of DIMMs from SIMMs to the various types of DIMMs (UDIMMs, RDIMMs, LRDIMMs, NVDIMMs, etc.)

  Module 9: Signal Routing
- Discusses basic signal routing rules and then walks through detailed examples of DDR4 fly-by routing for reads and writes
  Module 10: DDR4 - Bank State Machines, Commands and Waveforms
- Shows a detailed view of the DDR4 Bank States and discusses numerous state transitions, their motivations, behaviors, requirements, etc.; Contains a detailed table of DDR4 commands with descriptions; Walks through numerous DDR4 timing diagrams of various commands and provides insights for the motivations of behaviors and requirements; Also discusses burst orientations, types, lengths and order; Also discusses additive latency, NOP and power down
  Module 11: Refresh
- Provides a description of the different types of refresh and its history; Discusses important refresh timing parameters like Retention, Refresh Interval and Cycle Time; Describes the refresh command along with some newer forms of refresh (Temperature Controlled Refresh, Target Row Refresh, Refresh Management and Partial Array Refresh Control (PARC), and others), Row Hammer also discussed
 Module 12: DDR5, LPDDR4 and LPDDR5 Pin Descriptions
- Discusses Pin Groupings for DDR5, including additions/changes from DDR4; Similar discussion for LPDDR4 and LPDDR5 pin groupings
 Module 13: DDR5 Dual In-line Memory Modules
- Shows example diagrams of a 2 rank/channel DDR5 RDIMM and a 2 rank/channel DDR5 LRDIMM, also describes differences between UDIMMs and L/RDIMMs; Discusses DDR5 DIMM pinouts; DDR4 and DDR5 mirroring and inversion of command and address
 Module 14: DDR5 PMIC and the Sideband Bus
- Introduces the need for the Power Management IC (PMIC) and SidebandBus (I3C); explains limitations of I2C; shows several example systems and how PMICs and I3C fit in as well as typical communication with and behavior of PMICs
 Module 15: Non-Volatile DIMM Introduction
- Introduces NVDIMMs and the advantages / disadvantages of NVDIMMs vs other common DIMM types
 Module 16: DDR5 - Bank State Machines, Commands and Waveforms
- Detailed description of the DDR5 Bank states and the state transitions; Walks through the DDR5 commands and well as DDR5 burst order and behavior; Provides several examples of DDR5 command timing diagrams including DDR5 2N Mode
 Module 17: LPDDR4 - Bank State Machines, Commands and Waveforms
- Detailed description of the LPDDR4 Bank states and the state transitions; Walks through the LPDDR4 commands and provides several examples of LPDDR4 command timing diagrams including LPDDR4 MWR and DBI
 Module 18: LPDDR5 - Bank State Machines, Commands and Waveforms
- Detailed description of the LPDDR5 Bank states and the state transitions; Walks through the LPDDR5 commands and provides several examples of LPDDR5 command timing diagrams including WCK2CK Sync
 Module 19: Electrical Specifications
- Discusses numerous electrical aspects of modern DRAM including stub series-terminated logic, IDD current parameters, DDR5 IDD specs
 Module 20: Power Management
- Describes power down and self-refresh, numerous additional power savings modes, maximum power saving mode, clock throttling, frequency set points (FSP), dynamic voltage and frequency scaling (DVFSC and DVFSQ), Deep Sleep Mode
 Module 21: Signal Integrity Issues
- Discusses some of the most important items related to signal integrity
 Module 22: On-Die Termination
- Explains why ODT is needed and walks through the evolution of ODT for DRAM; Discusses ODT modes as well as Non-Target ODT (NT-ODT) and related mode registers
 Module 23: JEDEC Initialization
- Discusses the terms Initialization vs Training, SPD ROM location and format (with an example), mode registers and how to access, multi-purpose commands, Per-DRAM addressability (PDA); Goes through a detailed description of DDR 4 Mode Registers and Initialization process; Then walks through the steps for DDR5, LPDDR4 and LPDDR5 initialization as well
 Module 24: Calibration and Training
- Introduces the calibration features and then dives into ZQ calibration, Vref training, CA (Command Bus) training, duty cycle monitor and adjuster, read DQ calibration, write leveling, write calibration, FIFO-based training, DQS oscillator, Decision Feedback Equalization (DFE), DDR5 loopback
 Module 25: Errors and Error Handling
- Error Checking and Correction (ECC), DDR5 on-die ECC, ECC Error Check and Scrub (ECS), parity, CRC, post package repair (PPR), redundancy, guard key, Memory Built-In Self-Test (MBIST)
 Module 26: Testing
- JEDEC tools, types of tests and faults, structural testing, functional test, parametric and diagnostic tests, system, burn-in and stress tests, DDR4 and DDR5 connectivity test mode