PCIeGen3/Gen4/Gen5

Overview: This course provides a great overview of the basics of the PCI Express technology and is for individuals who need to know the fundamentals of PCI Express, It covers all the aspects of PCIe Gen1 to Gen4.

 Module 1: Introduction and Background 
- Describes the pieces of PCI relevant for PCIe as well as traditional traffic types and a typical transaction between an IO device and its device driver
 Module 2a: PCIe Architecture Overview
- Describes: Links, Lanes, Throughput, PCIe Topologies, Root Complexes, Endpoints, Switches, and example topologies
 Module 2b: PCIe Architecture Overview
- Provides an overview of flow control, Data Link Layer Packets (DLLPs), Ack/Nak protocol, framing of packets at Physical Layer, ordered set formats, and a review of electrical Physical Layer
 Module 2c: PCIe Architecture Overview
- Shows how the evolution of DRAM arrays and banks which leads into addressing data within a DRAM array; Defines banks, ranks and channels; Walks through the evolution of DRAM architecture (SDR, DDR1, DDR2, DDR3, DDR4, DDR4 and then on to LPDDR3, LPDDR4 and LPDDR5)
 Module 3: Configuration Space

- Provides an overview of legacy configuration space access mechanism as well as Enhanced Configuration Access Mechanism (ECAM), shows type 1 vs type 0 configuration headers, discusses legacy capability structures as well as extended capability structures and the linked list
 Module 4: Address Space Allocation
- Discusses prefetchable vs non-prefetchable MMIO, Base Address Registers (BARs) and how they request size and type of address space and how software allocates space to a BAR, how Base and Limit registers (address windows) are programmed by software and how a bridge interprets those values
  Module 5: Interrupt Support
- Brief introduction to legacy interrupt emulation as well as how Message Signaled Interrupts (MSIs) work in PCIe

  Module 6: Error Detection and Reporting
- Defines classes of errors: Correctable, Non-Fatal and Fatal as well as covers error reporting behaviors: PCI-compatible, baseline and Advanced Error Reporting (AER)
  Module 7: Power Management
- Introduces power states of a device (D0, D1, D2 and D3), power states of a link (L0, L0s, L1.0, L1.1, L1.2, L2, L3), discusses the relationship between device power states and link power states
  Module 8: Physical Layer - Logical
- Gives an introdcution to the logical portion of the Physical Layer for both 8b/10b speeds (2.5GT/s and 5.0GT/s) as well as 128b/130b speeds (8.0GT/s, 16.0GT/s and 32.0GT/s)
  Module 9: Physical Layer - Electrical
- Introduces differential signaling, de-emphasis, Tx equalization and the 3-tap equalizer
 Module 10: Link Initialization and Training
- Shows Training Sequence 1 and 2 (TS1 and TS2) ordered sets and a simplified view of the Link Training Status State Machine (LTSSM)
 Module 13: PCIe 4.0 and 5.0 Updates
- Discusses the purpose and behavior of Retimers, lane margining (both time margining and voltage margining) and a brief introduction to PCIe 5.0 updates.